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Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models., , , , and . CoRR, (2020)Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance., , , , and . ACM Great Lakes Symposium on VLSI, page 77-83. ACM, (2022)A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects., , , and . SMACD, page 89-92. IEEE, (2019)Electromigration Stress Analysis with Rational Krylov-based Approximation of Matrix Exponential., , , , and . SMACD, page 1-4. IEEE, (2023)Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis., , , , , and . DFT, page 1-6. IEEE, (2023)A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees Using Matrix Exponential., , , , and . ASP-DAC, page 1-6. ACM, (2023)EVT-based worst case delay estimation under process variation., , , and . DATE, page 1333-1338. IEEE, (2018)A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees using Matrix Exponential., , , , and . CoRR, (2022)Reduction of large-scale RLCk models via low-rank balanced truncation., , , and . CoRR, (2023)Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models., , , , and . ASP-DAC, page 773-778. ACM, (2021)