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A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory., , , , , , , , и . IEEE J. Solid State Circuits, 29 (11): 1366-1373 (ноября 1994)A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed., , , , , , , , , и 8 other автор(ы). IEEE J. Solid State Circuits, 32 (5): 670-680 (1997)Circuit techniques for a 1.8-V-only NAND flash memory., , , и . IEEE J. Solid State Circuits, 37 (1): 84-89 (2002)CP-PACS: A massively parallel processor at the University of Tsukuba., , , , и . Parallel Comput., 25 (13-14): 1635-1661 (1999)Grid as a bioinformatic tool., , , , , , , , и . Parallel Comput., 30 (9-10): 1093-1107 (2004)Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (4): 520-533 (2011)Inter-temperature Bandwidth Reduction in Cryogenic QAOA Machines., , , , , , и . CoRR, (2023)Adaptive Lossy Data Compression Extended Architecture for Memory Bandwidth Conservation in SpMV., , , , , и . IEICE Trans. Inf. Syst., 106 (12): 2015-2025 (декабря 2023)A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology., , , , , , , , , и 39 other автор(ы). IEEE J. Solid State Circuits, 55 (1): 178-188 (2020)Design and evaluation of fine-grained power-gating for embedded microprocessors., , , , , , , , , и 3 other автор(ы). DATE, стр. 1-6. European Design and Automation Association, (2014)