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Burst-Mode Asynchronous Controllers on FPGA., , and . Int. J. Reconfigurable Comput., (2008)Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions., , and . IDT, page 1-6. IEEE, (2013)On the Choice of Models of Computation for Writing Executable Specifications of System Level Designs., and . SBCCI, page 159-164. IEEE Computer Society, (2000)Formally verifying an RTOS scheduling monitor IP core in embedded systems., , , and . LATW, page 1-6. IEEE, (2011)BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional Units., , , and . LATW, page 64-69. IEEE, (2002)The LRD traffic impact on the NoC-based SoCs., , , and . SBCCI, page 97-102. ACM, (2010)A PD-based methodology to enhance efficiency in testbenches with random stimulation., , and . SBCCI, ACM, (2009)Exploring Concurrency in Data Path Functional Units BIST Plan Optimization: A Study-Case., , and . SBCCI, page 244-248. IEEE Computer Society, (1998)Hybrid-on-chip communication architecture for dynamic MP-SoC protection., , , , and . SBCCI, page 1-6. IEEE, (2012)The Multiple Pairs SMO: A modified SMO algorithm for the acceleration of the SVM training., , , and . IJCNN, page 1221-1228. IEEE Computer Society, (2009)