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Disambiguation of "Chiu, Pi-Feng"

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Improving Noise Tolerance of Hardware Accelerated Artificial Neural Networks.

, , , , and . ICMLA, page 797-801. IEEE, (2018)

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Yü Chih Chiu

Pi Huang

pi!1031782362!

Pi Ovaskainen

Chung-wai Chiu

 

Other publications of authors with the same name

A double-tail sense amplifier for low-voltage SRAM in 28nm technology., , and . A-SSCC, page 181-184. IEEE, (2016)Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements., , , , , and . IEEE J. Solid State Circuits, 45 (10): 2142-2155 (2010)Non-Volatile Memory Array Based Quantization- and Noise-Resilient LSTM Neural Networks., , , , , and . ICRC, page 25-33. IEEE, (2019)Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC., , , , , , , , , and 4 other author(s). ESSCIRC, page 269-272. IEEE, (2016)An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS., , , , and . VLSI Circuits, page 61-62. IEEE, (2018)Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor., , , and . A-SSCC, page 121-124. IEEE, (2016)Improving Noise Tolerance of Hardware Accelerated Artificial Neural Networks., , , , and . ICMLA, page 797-801. IEEE, (2018)A Differential 2R Crosspoint RRAM Array With Zero Standby Current., and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (5): 461-465 (2015)Reprogrammable Redundancy for SRAM-Based Cache Vmin Reduction in a 28-nm RISC-V Processor., , , and . IEEE J. Solid State Circuits, 52 (10): 2589-2600 (2017)BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS., , , , and . IEEE Micro, 39 (2): 52-60 (2019)