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High-level design environment for massive parallel VLSI-implementations of statistical signal- and image processing models.

, and . ISCAS (3), page 37-40. IEEE, (2004)

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High-level design environment for massive parallel VLSI-implementations of statistical signal- and image processing models., and . ISCAS (3), page 37-40. IEEE, (2004)Distributed, Event Driven Simulation of Spiking Neural Networks., and . NC, page 100-105. ICSC Academic Press, International Computer Science Conventions, Canada / Switzerland, (1998)On Actors and Objects - OOP in System Level Design., and . FDL, page 392-404. ECSI, (2004)VerCoLib: Fast and Versatile Communication for FPGAs via PCI Express., , and . ARC, volume 10824 of Lecture Notes in Computer Science, page 81-92. Springer, (2018)RACER - A Rapid Prototyping Accelerator for Pulsed Neural Networks., and . FCCM, page 277-278. IEEE Computer Society, (2002)