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Automated instrumentation of FPGA-based systems for system-level transaction monitoring., , and . SoC, page 168-171. IEEE, (2009)A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices., , and . SoCC, page 151-154. IEEE, (2008)Inferring Program Transformations from Type Transformations for Partitioning of Ordered Sets.. CoRR, (2015)Using type transformations to generate program variants for FPGA design space exploration., and . ReConFig, page 1-6. IEEE, (2015)MAW: A Reliable Lightweight Multi-hop Wireless Sensor Network Routing Protocol., , , and . CSE (2), page 487-493. IEEE Computer Society, (2009)A C++-embedded Domain-Specific Language for programming the MORA soft processor array., , , and . ASAP, page 141-148. IEEE Computer Society, (2010)Smart-Cache: Optimising Memory Accesses for Arbitrary Boundaries and Stencils on FPGAs., and . IPDPS Workshops, page 87-90. IEEE, (2019)An investigation into the feasibility and benefits of GPU/multicore acceleration of the weather research and forecasting model., and . HPCS, page 482-489. IEEE, (2013)A Hardware Relaxation Paradigm for Solving NP-Hard Problems., , , , and . BCS Int. Acad. Conf., page 75-86. British Computer Society, (2008)Twinned buffering: A simple and highly effective scheme for parallelization of Successive Over-Relaxation on GPUs and other accelerators., and . HPCS, page 436-443. IEEE, (2015)