( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Brain-inspired Cognition in Next-generation Racetrack Memories.

, , , , , и . ACM Trans. Embed. Comput. Syst., 21 (6): 79:1-79:28 (ноября 2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Janet Jones-Ullmann

Jens Olaf Jonescheit

Hugh Jones

Sara Jones

Arun W Jones

 

Другие публикации лиц с тем же именем

A Variable Length Coding Framework for Cost Function Reduction in Non-Volatile Memory Systems., , и . CoRR, (2017)A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks., , , , и . J. Parallel Distributed Comput., 65 (10): 1237-1252 (2005)Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories With PIETT., , , , , и . IEEE Trans. Computers, 72 (4): 1095-1109 (апреля 2023)Brain-inspired Cognition in Next-generation Racetrack Memories., , , , , и . ACM Trans. Embed. Comput. Syst., 21 (6): 79:1-79:28 (ноября 2022)Ordering circuit establishment in multiplane NoCs., , и . ACM Trans. Design Autom. Electr. Syst., 18 (4): 49:1-49:33 (2013)Efficient CAD development for emerging technologies using Objective-C and Cocoa., , и . ICECS, стр. 369-372. IEEE, (2004)EDA for extreme scale systems: design abstractions, metrics, and benchmarks.. ACM Great Lakes Symposium on VLSI, стр. 285-286. ACM, (2014)REFRESH FPGAs: Sustainable FPGA Chiplet Architectures., , , , , , , , и . CoRR, (2023)A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power., , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (11): 1250-1254 (2006)A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory., , , и . ISCAS, IEEE, (2006)