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Layout-aware gate duplication and buffer insertion.

, , and . DATE, page 1367-1372. EDA Consortium, San Jose, CA, USA, (2007)

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The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems., , , , and . Journal of Circuits, Systems, and Computers, 8 (1): 67-118 (1998)Synthesis of synchronous elastic architectures., , and . DAC, page 657-662. ACM, (2006)Timing-driven N-way decomposition., , and . ACM Great Lakes Symposium on VLSI, page 363-368. ACM, (2009)Petri Net Analysis Using Boolean Manipulation., , , and . Application and Theory of Petri Nets, volume 815 of Lecture Notes in Computer Science, page 416-435. Springer, (1994)Computing the full quotient in bi-decomposition by approximation., , , and . DATE, page 580-585. IEEE, (2020)A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (3): 409-422 (2014)A Scheduling Strategy for Synchronous Elastic Designs., , , and . Fundam. Informaticae, 108 (1-2): 1-21 (2011)State-Based Encoding of Large Asynchronous Controllers., and . IEEE Access, (2018)RTL-Aware Dataflow-Driven Macro Placement., , , , and . DATE, page 186-191. IEEE, (2019)Automatic microarchitectural pipelining., , , and . DATE, page 961-964. IEEE Computer Society, (2010)