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Design and Investigation of Configurable Source Coupled Logic., , and . ICM, page 283-286. IEEE, (2018)A 20Gb/s 40mW equalizer in 90nm CMOS technology., and . ISSCC, page 170-171. IEEE, (2010)A 112-fJ/bit 10-Gb/s Charge-Steering Equalizer Utilizing a Discrete-Time Linear Equalizer., , , and . MWSCAS, page 329-332. IEEE, (2020)A 10 Gbps ADC-based equalizer for serial I/O receiver., , and . IDT, page 38-43. IEEE, (2015)A fast-locking all-digital clock and data recovery circuit using successive approximation., and . MWSCAS, page 1-4. IEEE, (2016)Analysis, Modeling, and optimization of Single-Inductor Multiple-Output Continuous Conduction Mode Buck Converter with Arbitrary Number of Outputs., , and . ICM, page 177-180. IEEE, (2022)A low-power high-speed charge-steering ADC-based equalizer for serial links., , , and . ICECS, page 500-501. IEEE, (2015)A low-temperature-coefficient curvature-compensated bandgap reference with mismatch attenuation., , and . IDT, page 44-48. IEEE, (2015)Maximising return on investment (ROI) for pharmaceutical production., and . Int. J. Manuf. Technol. Manag., 24 (1/2/3/4): 167-181 (2011)A Low Power High PSR Wide Load LDO With Load-Dependent Feedforward Cancellation Technique., , and . MWSCAS, page 216-219. IEEE, (2021)