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A Timed Petri Net Approach for Pre-Runtime Scheduling in Partial and Dynamic Reconfigurable Systems.

, , , , , and . IPDPS, IEEE Computer Society, (2005)

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FPGA Implementation of the Generalized Delayed Signal Cancelation - Phase Locked Loop Method for Detecting Harmonic Sequence Components in Three-Phase Signals., , , and . IEEE Trans. Ind. Electron., 60 (2): 645-658 (2013)A partial reconfigurable architecture for controllers based on Petri nets., , , , and . SBCCI, page 16-21. ACM, (2004)Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration., , , and . SBCCI, page 50-55. ACM, (2006)Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures., and . DATE, page 375-380. European Design and Automation Association, Leuven, Belgium, (2006)A petri-net based Pre-runtime scheduler for dynamically self-reconfiguration of FPGAs (abstract only)., , , , , and . FPGA, page 262. ACM, (2005)FPGA design methodology for DSP industrial applications - A case study of a three-phase positive-sequence detector., , , and . SBCCI, page 1-6. IEEE, (2012)CDFG -Petri Net Temporal Partitioning for Switching Context Applications., , and . SBCCI, page 235-242. IEEE Computer Society, (2002)A Timed Petri Net Approach for Pre-Runtime Scheduling in Partial and Dynamic Reconfigurable Systems., , , , , and . IPDPS, IEEE Computer Society, (2005)Aquarius: a dynamically reconfigurable computing platform., , , , , , , and . SBCCI, page 171-176. ACM, (2007)A partial reconfigurable FPGA implementation for industrial controllers using SFC-petri net description (abstract only)., , , , and . FPGA, page 275. ACM, (2005)