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A high performance hardware architecture for portable, low-power retinal vessel segmentation.

, , , and . Integr., 47 (3): 377-386 (2014)

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Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms., and . VLSI Design, (2012)In-field vulnerability analysis of hardware-accelerated computer vision applications., , , , and . FPL, page 1-4. IEEE, (2015)A high performance hardware architecture for portable, low-power retinal vessel segmentation., , , and . Integr., 47 (3): 377-386 (2014)FPGA-based NoC-driven sequence of lab assignments for manycore systems., , , and . MSE, page 5-8. IEEE Computer Society, (2009)A laboratory course on 3D vision for robotic applications., , , , and . MSE, page 21-24. IEEE Computer Society, (2013)A reconfigurable MPSoC-based QAM modulation architecture., , , , and . VLSI-SoC, page 137-142. IEEE, (2010)Hardware acceleration of retinal blood vasculature segmentation., , and . ACM Great Lakes Symposium on VLSI, page 113-118. ACM, (2013)Real-Time Obstacle Avoidance for Mobile Robots via Stereoscopic Vision Using Reconfigurable Hardware (Abstract Only)., , , and . FPGA, page 262. ACM, (2015)An MPSoC-Based QAM Modulation Architecture with Run-Time Load-Balancing., , , , and . EURASIP J. Embed. Syst., (2011)A Hardware-Efficient Architecture for Accurate Real-Time Disparity Map Estimation., , and . ACM Trans. Embed. Comput. Syst., 14 (2): 36:1-36:26 (2015)