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Reliability of Mo as Word Line Metal in 3D NAND., , , , , and . IRPS, page 1-6. IEEE, (2021)An easy-to-use mismatch model for the MOS transistor., , , , and . IEEE J. Solid State Circuits, 37 (8): 1056-1064 (2002)Development of Gated Pinned Avalanche Photodiode Pixels for High-Speed Low-Light Imaging., , , , , , and . Sensors, 16 (8): 1294 (2016)Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification., , , , , , , and . Sensors, 18 (11): 3683 (2018)A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics., , , , , , , , and . IMW, page 1-4. IEEE, (2021)Characterization of charge trapping in SiO2/Al2O3 dielectric stacks by pulsed C-V technique., , , , and . Microelectron. Reliab., 47 (4-5): 508-512 (2007)Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND., , , , , , , and . IMW, page 1-4. IEEE, (2023)At the Extreme of 3D-NAND Scaling: 25 nm Z-Pitch with 10 nm Word Line Cells., , , , , , , , and . IMW, page 1-4. IEEE, (2022)Enabling 3D NAND Trench Cells for Scaled Flash Memories., , , , , , , , and . IMW, page 1-4. IEEE, (2023)Improved MW of IGZO-channel FeFET by Reading Scheme Optimization and Interfacial Engineering., , , , , , , , , and . IMW, page 1-4. IEEE, (2023)