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Disambiguation of "Na, Myung Hee"

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A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration.

, , , , , , , and . CICC, page 1-2. IEEE, (2021)

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Myung Hee Jung

Myung-Hee Chung

Myung-Hee Oh

Nam-Jin Myung

Jae Jin Myung

 

Other publications of authors with the same name

The chalcogenide-based memory technology continues: beyond 20nm 4-deck 256Gb cross-point memory., , , , , , , , , and 4 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)QLC Programmable 3D Ferroelectric NAND Flash Memory by Memory Window Expansion using Cell Stack Engineering., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration., , , , , , , and . ISCAS, page 1-5. IEEE, (2021)Structural and Device Considerations for Vertical Cross Point Memory with Single-stack Memory toward CXL Memory beyond 1x nm 3DXP., , , , , , , , , and 2 other author(s). IMW, page 1-4. IEEE, (2022)Memory Window Expansion for Ferroelectric FET based Multilevel NVM: Hybrid Solution with Combination of Polarization and Injected Charges., , , , , , , , , and 1 other author(s). IMW, page 1-4. IEEE, (2022)A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration., , , , , , , and . CICC, page 1-2. IEEE, (2021)Demonstration of crystalline IGZO transistor with high thermal stability for memory applications., , , , , , , , , and 3 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Recognition Accuracy Enhancement using Interface Control with Weight Variation-Lowering in Analog Computation-in-Memory., , , , , , , , , and 6 other author(s). IMW, page 1-3. IEEE, (2022)