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Disambiguation of "Reorda, Matteo Sonza"

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An effective approach to automatic functional processor test generation for small-delay faults.

, , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)

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Matteo Garavoglia

Marco Matteo

Matteo Rini

Matteo Bertini

Matteo Gabba

 

Other publications of authors with the same name

BASTION: Board and SoC test instrumentation for ageing and no failure found., , , , , , , , and . DATE, page 115-120. IEEE, (2017)Software-Based Self-Test for Transition Faults: a Case Study., , , and . VLSI-SoC, page 76-81. IEEE, (2019)A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks., , , and . IEEE Trans. Computers, 69 (1): 87-98 (2020)Test-Plan Optimization for Flying-Probes In-Circuit Testers., , , and . ITC-Asia, page 19-24. IEEE, (2019)New techniques for efficiently assessing reliability of SOCs., , , , and . Microelectron. J., 34 (1): 53-61 (2003)Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs., , , , and . J. Electron. Test., 23 (1): 47-54 (2007)GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (8): 991-1000 (1996)Guest Editors' Introduction: SBCCI 2019., and . IEEE Des. Test, 38 (4): 60-61 (2021)DYRE: a DYnamic REconfigurable solution to increase GPGPU's reliability., , , and . J. Supercomput., 77 (10): 11625-11642 (2021)Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug., , , and . IET Comput. Digit. Tech., 4 (2): 104-113 (2010)