( en | de | ru )

 

Disambiguation of "Sim, Jae-Yoon"

Author of the publication

copydeleteadd this publication to your clipboard
A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS.

, , , , and . ISSCC, page 482-483. IEEE, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jae-Han Sim

Jae-Yoon Kim

Sim Hägele

Unyong Sim

Gavin Sim

 

Other publications of authors with the same name

A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor., , , , , , , , and . IEEE J. Solid State Circuits, 38 (4): 631-640 (2003)Low-Noise Distributed RC Oscillator., and . IEEE Trans. Very Large Scale Integr. Syst., 30 (2): 143-152 (2022)A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme., , , , , and . IEEE J. Solid State Circuits, 37 (2): 245-250 (2002)Multipurpose Deep-Learning Accelerator for Arbitrary Quantization With Reduction of Storage, Logic, and Latency Waste., , , and . IEEE J. Solid State Circuits, 59 (1): 143-156 (January 2024)Analysis and prevention of DRAM latch-up during power-on., , , , , , , , and . IEEE J. Solid State Circuits, 32 (1): 79-85 (1997)A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines., , , , and . IEEE J. Solid State Circuits, 47 (9): 2068-2079 (2012)A 26GHz Fractional-N Digital Frequency Synthesizer Leveraging Noise Profiles of Three Functional Stages., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (9): 3063-3067 (2021)A 384G Output NonZeros/J Graph Convolutional Neural Network Accelerator., , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (10): 4158-4162 (2022)A 2.5Gbps Transceiver and Channel Architecture for High-Speed Automotive Communication System., and . IEICE Trans. Electron., 102-C (10): 766-769 (2019)Bottleneck-Stationary Compact Model Accelerator With Reduced Requirement on Memory Bandwidth for Edge Applications., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (2): 772-782 (February 2023)