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Disambiguation of "Saha, Prabir"

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Implementation of high speed processor for computing convolution sum for DSP applications.

, , and . IMCOM, page 51:1-51:6. ACM, (2015)

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Prabir Dutt

Janapriya Saha

Susanne Saha

Sankalita Saha

Joyanta Saha

 

Other publications of authors with the same name

Minimizing Ancilla Inputs and Garbage Outputs of Reversible BCD Multiplier., and . J. Circuits Syst. Comput., 31 (4): 2250062:1-2250062:23 (2022)Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications., , , and . ISED, page 41-45. IEEE Computer Society, (2013)Design of High Speed Vedic Multiplier for Decimal Number System., , , and . VDAT, volume 7373 of Lecture Notes in Computer Science, page 79-88. Springer, (2012)Modeling of Threshold Voltage and Subthreshold Current for P-Channel Symmetric Double-Gate MOSFET in Nanoscale Regime., and . iNIS, page 179-183. IEEE, (2017)ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics., , , and . Microelectron. J., 42 (12): 1343-1352 (2011)Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation., and . Period. Polytech. Electr. Eng. Comput. Sci., (2020)Implementation of high speed processor for computing convolution sum for DSP applications., , and . IMCOM, page 51:1-51:6. ACM, (2015)A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder., and . Period. Polytech. Electr. Eng. Comput. Sci., 64 (4): 343-351 (2020)Improved matrix multiplier design for high-speed digital signal processing applications., , , and . IET Circuits Devices Syst., 8 (1): 27-37 (2014)Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication., , , and . Integr., (January 2024)