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How Bad Are Bad Templates? Optimistic Design-Stage Side-Channel Security Evaluation and its Cost., and . Cryptogr., 4 (4): 36 (2020)A security oriented transient-noise simulation methodology: Evaluation of intrinsic physical noise of cryptographic designs., , , , and . Integr., (2019)Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (10): 2180-2184 (2018)Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable Side Information., , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (1): 82-95 (2018)Modular Processor Architecture with Cryptography ISA Extensions., and . NEWCAS, page 1-2. IEEE, (2023)FPGA Implementation of pAsynch Design Paradigm., , , and . NTMS, page 1-5. IEEE, (2019)Reducing a Masked Implementation's Effective Security Order with Setup Manipulations And an Explanation Based on Externally-Amplified Couplings., , and . IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019 (2): 293-317 (2019)An 88-fJ/40-MHz 0.4 V-0.61-pJ/1-GHz 0.9 V Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI., , , and . IEEE J. Solid State Circuits, 54 (2): 560-568 (2019)Hardware Private Circuits: From Trivial Composition to Full Verification., , , and . IEEE Trans. Computers, 70 (10): 1677-1690 (2021)An In-Depth Evaluation of Externally Amplified Coupling (EAC) Attacks - A Concrete Threat for Masked Cryptographic Implementations., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (2): 783-796 (February 2023)