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At-speed capture global noise reduction & low-power memory test architecture.

B. Bhaskaran, S. Chadalavada, S. Sarangi, N. Valentine, V. Nerallapally, and A. Abdollahian. VTS, page 1-6. IEEE Computer Society, (2017)

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Bonita Hoffmann

Bonita Brodhun

Other publications of authors with the same name

Fault Modeling and Testability of CMOS Domino Circuits.W. Al-Assadi, P. Chandrasekhar, and B. Bhaskaran. CDES, page 21-27. CSREA Press, (2005)Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms.P. Jagannadha, M. Yilmaz, M. Sonawane, S. Chadalavada, S. Sarangi, B. Bhaskaran, S. Bajpai, V. Nerallapally, J. Pandey, and S. Jiang. VTS, page 1-8. IEEE, (2019)Automated energy calculation and estimation for delay-insensitive digital circuits.V. Satagopan, B. Bhaskaran, A. Singh, and S. Smith. Microelectron. J., 38 (10-11): 1095-1107 (2007)Observation Point Insertion Using Deep Learning.B. Bhaskaran, S. Banerjee, K. Narayanun, S. Hung, S. Mojaveri, M. Liu, G. Chen, and T. Liang. ICCAD, page 161:1-161:8. ACM, (2022)A Novel Graph Coloring Based Solution for Low-Power Scan Shift.S. Gupta, B. Bhaskaran, S. Sarangi, A. Abdollahian, and J. Dworak. VTS, page 1-6. IEEE, (2019)Test method and scheme for low-power validation in modern SOC integrated circuits.B. Bhaskaran, A. Sanghani, K. Narayanun, A. Abdollahian, and A. Laknaur. VTS, page 1-6. IEEE Computer Society, (2016)On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST).S. Mozaffari, B. Bhaskaran, S. Sarangi, S. Satheesh, K. Fu, N. Valentine, P. Manikandan, and M. Yilmaz. VTS, page 1-6. IEEE, (2022)High-Speed Energy Estimation for Delay-Insensitive Circuits.B. Bhaskaran, V. Satagopan, and S. Smith. CDES, page 35-41. CSREA Press, (2005)Implementation of Design For Test for Asynchronous NCL Designs.B. Bhaskaran, V. Satagopan, W. Al-Assadi, and S. Smith. CDES, page 78-84. CSREA Press, (2005)DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits.V. Satagopan, B. Bhaskaran, W. Al-Assadi, S. Smith, and S. Kakarla. IEEE Trans. Very Large Scale Integr. Syst., 15 (10): 1155-1159 (2007)

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Disambiguation of "Bhaskaran, Bonita"

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At-speed capture global noise reduction & low-power memory test architecture.

Please choose a person to relate this publication to

Bonita Hoffmann

Bonita Brodhun

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Bhaskaran, Bonita"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML At-speed capture global noise reduction & low-power memory test architecture.

Please choose a person to relate this publication to

Bonita Hoffmann

Bonita Brodhun

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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At-speed capture global noise reduction & low-power memory test architecture.