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Disambiguation of "Miwa, Shinobu"

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RPC: An Approach for Reducing Compulsory Misses in Packet Processing Cache.

, , , and . IEICE Trans. Inf. Syst., 103-D (12): 2590-2599 (2020)

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Other publications of authors with the same name

Evaluation of Core Hopping on POWER7., and . SIGMETRICS Perform. Evaluation Rev., 42 (3): 55-60 (2014)Multi-Level Packet Processing Caches., , , and . COOL CHIPS, page 1-3. IEEE, (2019)PredCom: A Predictive Approach to Collecting Approximated Communication Traces., , and . IEEE Trans. Parallel Distributed Syst., 32 (1): 45-58 (2021)Footprint-Based DIMM Hotplug., , , , and . IEEE Trans. Computers, 69 (2): 172-184 (2020)Functionally-Predefined Kernel: a Way to Reduce CNN Computation., , , and . PACRIM, page 1-6. IEEE, (2019)CNFET7: An Open Source Cell Library for 7-nm CNFET Technology., , , , , and . ASP-DAC, page 763-768. ACM, (2023)McRouter: Multicast within a router for high performance network-on-chips., , , and . PACT, page 319-329. IEEE Computer Society, (2013)Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches., , , , , , and . ICCD, page 149-156. IEEE Computer Society, (2015)Normally-off computing project: Challenges and opportunities., , and . ASP-DAC, page 1-5. IEEE, (2014)A novel power-gating scheme utilizing data retentiveness on caches., , , and . ACM Great Lakes Symposium on VLSI, page 91-94. ACM, (2012)