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Application-oriented cache memory configuration for energy efficiency in multi-cores.

, , , , and . IET Comput. Digit. Tech., 9 (1): 73-81 (2015)

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Application-oriented cache memory configuration for energy efficiency in multi-cores., , , , and . IET Comput. Digit. Tech., 9 (1): 73-81 (2015)A FAST Hardware Decoder Optimized for Template Features to Obtain Order Book Data in Low Latency., and . J. Signal Process. Syst., 95 (4): 559-567 (April 2023)Order book mid-price movement inference by CatBoost classifier from convolutional feature maps., , , and . Appl. Soft Comput., (2022)Designing FPGA-based embedded systems with MARTE: A PIM to PSM converter., , and . IECON, page 4682-4687. IEEE, (2012)Scaling Up Modulo Scheduling for High-Level Synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (5): 912-925 (2019)Scaling Up Loop Pipelining for High-Level Synthesis: A Non-iterative Approach., , and . FPT, page 62-69. IEEE, (2018)Lina: Timing-Constrained High-Level Synthesis Performance Estimator for Fast DSE., , and . FPT, page 343-346. IEEE, (2019)Class-specific early exit design methodology for convolutional neural networks., and . Appl. Soft Comput., (2021)Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis., , , and . IEEE Trans. Computers, 70 (12): 2070-2082 (2021)Non-iterative SDC modulo scheduling for high-level synthesis., , and . Microprocess. Microsystems, (October 2021)