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Congestion-aware memory management on NUMA platforms: A VMware ESXi case study.

, , , and . IISWC, page 146-155. IEEE Computer Society, (2017)

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Reducing Energy Consumption in Chip Multiprocessors Using Workload Variations., , , , and . Ultra Low-Power Electronics and Design, Kluwer / Springer, (2004)TaPEr: tackling power emergencies in the dark silicon era by exploiting resource scalability., , and . Conf. Computing Frontiers, page 16:1-16:8. ACM, (2015)Hybrid-comp: A criticality-aware compressed last-level cache., , , and . ISQED, page 25-30. IEEE, (2018)Compilation for Distributed Memory Architectures., and . The Compiler Design Handbook, CRC Press, (2002)The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense., , , , , and . IJDSN, 2 (3): 267-287 (2006)Leveraging value locality for efficient design of a hybrid cache in multicore processors., , , and . ICCAD, page 1-8. IEEE, (2017)Using data replication to reduce communication energy on chip multiprocessors., , , and . ASP-DAC, page 769-772. ACM Press, (2005)Optimizing embedded applications using programmer-inserted hints., and . ASP-DAC, page 157-160. ACM Press, (2005)FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads., , and . HPCA, page 426-439. IEEE, (2019)Performance aware secure code partitioning., , and . DATE, page 1122-1127. EDA Consortium, San Jose, CA, USA, (2007)