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Buffer Insertion and Sizing in Clock Distribution Networks with Gradual Transition Time Relaxation for Reduced Power Consumption.

, and . ICECS, page 845-848. IEEE, (2007)

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Underlap engineered eight-transistor SRAM cell for stronger data stability enhanced write ability and suppressed leakage power consumption., and . ICECS, page 25-28. IEEE, (2013)Temperature-Adaptive Energy Reduction for Ultra-Low Power-Supply-Voltage Subthreshold Logic Circuits., and . ICECS, page 1280-1283. IEEE, (2007)Impact of temperature fluctuations on circuit characteristics in 180nm and 65nm CMOS technologies., and . ISCAS, IEEE, (2006)Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide Tunneling., and . SoCC, page 151-154. IEEE, (2005)Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode., , and . Integr., (2016)Low Power and High Speed Multi Threshold Voltage Interface Circuits., and . IEEE Trans. Very Large Scale Integr. Syst., 17 (5): 638-645 (2009)Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits., and . IEEE Trans. Very Large Scale Integr. Syst., 21 (3): 533-545 (2013)Low power and robust memory circuits with asymmetrical ground gating., , and . Microelectron. J., (2016)Voltage optimization for simultaneous energy efficiency and temperature variation resilience in CMOS circuits., and . Microelectron. J., 38 (4-5): 583-594 (2007)Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits., and . Microelectron. J., 39 (12): 1714-1727 (2008)