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Error resilience of intra-die and inter-die communication with 3D spidergon STNoC.

, , , , and . DATE, page 275-278. IEEE Computer Society, (2010)

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Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead., , , , , and . IEEE Trans. Computers, 63 (3): 557-569 (2014)EEEP: an extreme end to end flow control protocol for SDRAM access through networks on chip., , , and . INA-OCMC@HiPEAC, page 3-6. ACM, (2011)Spidergon: a novel on-chip communication network., , , , and . SoC, IEEE, (2004)A reusable coverage-driven verification environment for Network-on-Chip communication in embedded system platforms., , , , , , , and . WISES, page 71-77. IEEE, (2009)Application-Specific Topology Design Customization for STNoC., , , , and . DSD, page 547-550. IEEE Computer Society, (2007)Coverage-Driven Verification of HDL IP Cores - Case Study of a Router for Network-on-Chip Communication in Embedded Systems., , , , , and . Solutions on Embedded Systems, volume 81 of Lecture Notes in Electrical Engineering, Springer, (2011)RFI Cancellation in DMT VDSL: A Digital Frequency Domain Scheme., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (8): 1993-2000 (2003)Design and Implementation on FPGA of a HW Accelerator for Post-Quantum RLWE Polynomial Operations., , and . ApplePies, volume 1036 of Lecture Notes in Electrical Engineering, page 57-64. Springer, (2022)Skew Insensitive Physical Links for Network on Chip., , , , , , , and . Nano-Net, page 1-5. IEEE, (2006)Error resilience of intra-die and inter-die communication with 3D spidergon STNoC., , , , and . DATE, page 275-278. IEEE Computer Society, (2010)