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Formal Verification Using Edge-Valued Binary Decision Diagrams.

, , and . IEEE Trans. Computers, 45 (2): 247-255 (1996)

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Fast and robust differential flipflops and their extension to multi-input threshold gates., , , and . ISCAS, page 822-825. IEEE, (2015)Formal Verification Using Edge-Valued Binary Decision Diagrams., , and . IEEE Trans. Computers, 45 (2): 247-255 (1996)CAMDNN: Content-Aware Mapping of a Network of Deep Neural Networks on Edge MPSoCs., , , , and . IEEE Trans. Computers, 71 (12): 3191-3202 (2022)Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (2): 424-437 (2020)Statistical waveform and current source based standard cell models for accurate timing analysis., and . DAC, page 227-230. ACM, (2008)Throughput optimal task allocation under thermal constraints for multi-core processors., , , and . DAC, page 776-781. ACM, (2009)A fast, energy efficient, field programmable threshold-logic array., , and . FPT, page 300-305. IEEE, (2014)Statistical library characterization using arbitrary polynomial chaos., , and . LASCAS, page 1-4. IEEE, (2017)ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler., , , , and . Integr., (2018)The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (2): 173-183 (2010)