Author of the publication

Integrated circuit-architectural framework for PSN aware floorplanning in microprocessors.

, , and . ISQED, page 212-218. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (3): 512-522 (2012)Dynamic Choke Sensing for Timing Error Resilience in NTC Systems., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (1): 1-10 (2018)Security Measures Against a Rogue Network-on-Chip., , , and . J. Hardw. Syst. Secur., 1 (2): 173-187 (2017)Securing Data Center Against Power Attacks., , , and . J. Hardw. Syst. Secur., 3 (2): 177-188 (2019)TASPDetect: Reviving Trust in 3PIP By Detecting TASP Trojans., , , , and . Microprocess. Microsystems, (2018)Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm., , , and . ACM Trans. Design Autom. Electr. Syst., 16 (3): 23:1-23:21 (2011)Exploring Warp Criticality in Near-Threshold GPGPU Applications Using a Dynamic Choke Point Analysis., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (2): 456-466 (2020)A Novel Threshold Voltage Assignment for 3D Multicore Designs., and . J. Low Power Electron., 6 (3): 436-446 (2010)BoostNoC: power efficient network-on-chip architecture for near threshold computing., , , and . ICCAD, page 124. ACM, (2016)Analysis of intermittent timing fault vulnerability., , , and . Microelectron. Reliab., 52 (7): 1515-1522 (2012)