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Disambiguation of "Blaauw, David T."

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A Reliable Routing Architecture and Algorithm for NoCs.

, , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (5): 726-739 (2012)

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Konrad Blaauw

Gilles Jan Blaauw

Ruth Meier-Blaauw

T Attin

T Neumann

 

Other publications of authors with the same name

Automatic Generation of Behavioral Models from Switch-Level Descriptions., , , , and . DAC, page 179-184. ACM Press, (1989)A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS., , , , and . VLSIC, page 270-. IEEE, (2015)In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter., , , , , , and . ISSCC, page 188-189. IEEE, (2010)A 467nW CMOS visual motion sensor with temporal averaging and pixel aggregation., , , , , , and . ISSCC, page 480-481. IEEE, (2013)A Charge-Injection-Based Active-Decoupling Technique for Inductive-Supply-Noise Suppression., and . ISSCC, page 416-417. IEEE, (2008)DVS for On-Chip Bus Designs Based on Timing Error Correction, , , , and . CoRR, (2007)Energy Efficient Adiabatic FRAM with 0.99 PJ/Bit Write for IoT Applications., , , , , , and . VLSI Circuits, page 85-86. IEEE, (2018)Circuit optimization techniques to mitigate the effects of soft errors in combinational logic., , , and . ACM Trans. Design Autom. Electr. Syst., 15 (1): 5:1-5:27 (2009)A library compatible driving point model for on-chip RLC interconnects., , and . Timing Issues in the Specification and Synthesis of Digital Systems, page 63-69. ACM, (2002)Active shielding of RLC global interconnects., , and . Timing Issues in the Specification and Synthesis of Digital Systems, page 98-104. ACM, (2002)