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Disambiguation of "Venkatesan, Rangharajan"

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Reading spin-torque memory with spin-torque sensors.

, , , , and . NANOARCH, page 40-41. IEEE Computer Society, (2013)

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Venkatesan Guruswami

Chandrasekara Venkatesan

Radhika Venkatesan

Aravind Venkatesan

Venkatesan Guruswami

 

Other publications of authors with the same name

Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training., , , , , and . ICML, volume 162 of Proceedings of Machine Learning Research, page 19123-19138. PMLR, (2022)DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes., , , and . DATE, page 1825-1830. EDA Consortium San Jose, CA, USA / ACM DL, (2013)VESPA: Variability emulation for System-on-Chip performance analysis., , , and . DATE, page 2-7. IEEE, (2011)Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update., , , , , , and . CoRR, (2021)SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing., , , , and . ISLPED, page 15-20. ACM, (2014)A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm., , , , , , , and . VLSI Technology and Circuits, page 16-17. IEEE, (2022)Reading spin-torque memory with spin-torque sensors., , , , and . NANOARCH, page 40-41. IEEE Computer Society, (2013)STAxCache: An approximate, energy efficient STT-MRAM cache., , , , , and . DATE, page 356-361. IEEE, (2017)A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology., , , , , , , , , and 7 other author(s). Hot Chips Symposium, page 1-24. IEEE, (2019)VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference., , , , , and . MLSys, mlsys.org, (2021)