Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A BIST Design of Structured Arrays with Fault-Tolerant Layout., and . ITC, page 514-521. IEEE Computer Society, (1988)An equivalent-time and clocked approach for continuous-time quantization., , , , , , , and . ISCAS, page 2529-2532. IEEE, (2011)Mismatch-Tolerant Circuit for On-Chip Measurements of Data Jitter., , , and . CICC, page 161-164. IEEE, (2007)Mixed-signal on-chip timing measurements.. Integr., 26 (1-2): 151-165 (1998)Test set selection for structural faults in analog IC's., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (7): 1026-1039 (1999)Hierarchical ATPG for Analog Circuits and Systems., , , , and . IEEE Des. Test Comput., 18 (1): 72-81 (2001)Extraction of instantaneous and RMS sinusoidal jitter using an analytic signal method., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (6): 288-298 (2003)Minimal overhead modification of iterative logic arrays for C-testability., and . ITC, page 964-969. IEEE Computer Society, (1990)Dynamic Testing of ADCs Using Wavelet Transforms., and . ITC, page 379-388. IEEE Computer Society, (1997)Analytical fault modeling and static test generation for analog ICs., and . ICCAD, page 44-47. IEEE Computer Society / ACM, (1994)