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Disambiguation of "Garcia-Herrero, Francisco"

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A 630 Mbps non-binary LDPC decoder for FPGA.

, , , , and . ISCAS, page 1989-1992. IEEE, (2015)

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Julio Herrero García

Francisco Herrero Martin

Francisco Orengo Garcia

Francisco Hita Garcia

Francisco García Moreno

 

Other publications of authors with the same name

Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes., , , and . IEEE Communications Letters, 16 (6): 909-912 (2012)High-Speed RS(255, 239) Decoder Based on LCC Decoding., , and . CSSP, 30 (6): 1643-1669 (2011)Non-Binary LDPC Decoder Based on Symbol Flipping with Multiple Votes., , and . IEEE Communications Letters, 18 (5): 749-752 (2014)Low-Complexity Linear Programming Based Decoding of Quantum LDPC codes., , , and . CoRR, (2023)Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm., , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (6): 1455-1459 (2014)Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes., , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (9): 1783-1792 (2015)High-Performance NB-LDPC Decoder With Reduction of Message Exchange., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1950-1961 (2016)Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase., , and . IEEE Trans. Circuits Syst., 67-II (12): 3362-3366 (2020)Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes., , , and . IEEE Access, (2021)Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs., , , and . IEEE Access, (2021)