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Hardware and Software Techniques for Controlling DRAM Power Modes., , , , and . IEEE Trans. Computers, 50 (11): 1154-1173 (2001)Modeling steep slope devices: From circuits to architectures., , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Influence of compiler optimizations on system power., , , and . DAC, page 304-307. ACM, (2000)A low latency router supporting adaptivity for on-chip interconnects., , , , and . DAC, page 559-564. ACM, (2005)Design and analysis of an NoC architecture from performance, reliability and energy perspective., , , , and . ANCS, page 173-182. ACM, (2005)Design space exploration of workload-specific last-level caches., , , , and . ISLPED, page 243-248. ACM, (2012)Editorial., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (1): 1 (2015)AutoFLEX: A Framework for Image Processing Applications on Multiple-FPGA Systems., , , , and . ERSA, page 59-66. CSREA Press, (2010)Programmable Non-Volatile Memory Design Featuring Reconfigurable In-Memory Operations., , , , and . ISCAS, page 1-5. IEEE, (2019)A Dual-VDD Low Power FPGA Architecture., , , , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 145-157. Springer, (2004)