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Sensitivity of interconnect delay to on-chip inductance., and . ISCAS, page 403-406. IEEE, (2000)On-chip inductance cons and pros.. IEEE Trans. Very Large Scale Integr. Syst., 10 (6): 685-694 (2002)A CMOS based operational floating current conveyor., , , and . ICECS, page 157-160. IEEE, (2015)FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling., , , , and . ICCD, page 43-49. IEEE, (2006)Emitter-coupled spin-transistor logic., , , , and . NANOARCH, page 139-145. ACM, (2012)Weibull Based Analytical Waveform Model., , and . ICCAD, page 161-168. IEEE Computer Society / ACM, (2003)Serial-link bus: a low-power on-chip bus architecture., , , , and . ICCAD, page 541-546. IEEE Computer Society, (2005)On the Extraction of On-Chip Inductance., and . Journal of Circuits, Systems, and Computers, 12 (1): 31-40 (2003)Equivalent Elmore Delay for RLC Trees., , and . DAC, page 715-720. ACM Press, (1999)Low power coupling-based encoding for on-chip buses., and . ISCAS (2), page 325-328. IEEE, (2004)