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Software Approaches for In-time Resilience., and . DAC, page 197. ACM, (2019)A Gate Level Analysis of Transient Faults Effects on Dual-Core Chip-Multi Processors., , , and . ARES, page 365-370. IEEE Computer Society, (2011)Software Techniques For Dependable Execution.. Arizona State University, Tempe, USA, (2018)base-search.net (ftarizonastateun:item:51604).InCheck: An In-application Recovery Scheme for Soft Errors., , and . DAC, page 40:1-40:6. ACM, (2017)A software-level Redundant MultiThreading for Soft/Hard Error Detection and Recovery., , , and . DATE, page 1559-1562. IEEE, (2019)Generic Soft Error Data and Control Flow Error Detection by Instruction Duplication., , , , and . IEEE Trans. Dependable Secur. Comput., 21 (1): 78-92 (January 2024)CHITIN: A Comprehensive In-thread Instruction Replication Technique Against Transient Faults., , , , and . DATE, page 1440-1445. IEEE, (2021)EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults., , , , and . ACM Trans. Archit. Code Optim., 19 (4): 53:1-53:26 (2022)NEMESIS: A software approach for computing in presence of soft errors., , and . ICCAD, page 297-304. IEEE, (2017)A Compiler Technique for Processor-Wide Protection From Soft Errors in Multithreaded Environments., and . IEEE Trans. Reliab., 67 (1): 249-263 (2018)