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Synthesis of delay fault testable combinational logic.

, , , and . ICCAD, page 418-421. IEEE Computer Society, (1989)

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Accurate pre-layout estimation of standard cell characteristics., , and . DAC, page 208-211. ACM, (2004)Logic Partitioning and Resynthesis for Testability., and . ITC, page 906-915. IEEE Computer Society, (1991)Abstract: PanDA: Next Generation Workload Management and Analysis System for Big Data., , , , , , , and . SC Companion, page 1521-1522. IEEE Computer Society, (2012)PanDA: Production and Distributed Analysis System., , , , , , , , , and 3 other author(s). Comput. Softw. Big Sci., 8 (1): 4 (December 2024)Workflows Community Summit: Advancing the State-of-the-art of Scientific Workflows Management Systems Research and Development., , , , , , , , , and 48 other author(s). CoRR, (2021)Parallel algorithms for logic synthesis using the MIS approach., , , , and . IPPS, page 579-585. IEEE Computer Society, (1995)Test methodology for embedded cores which protects intellectual property.. VTS, page 2-9. IEEE Computer Society, (1997)Failure Analysis for Full-Scan Circuits., and . ITC, page 636-645. IEEE Computer Society, (1995)Poster: PanDA: Next Generation Workload Management and Analysis System for Big Data., , , , , , , and . SC Companion, page 1523. IEEE Computer Society, (2012)A portable parallel algorithm for logic synthesis using transduction., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (5): 566-580 (1994)