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Disambiguation of "Miniskar, Narasinga Rao"

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Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study.

, , , , , and . SAMOS, volume 5657 of Lecture Notes in Computer Science, page 48-57. Springer, (2009)

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Boloor Ramananda Rao

Nagaraj Narayan Rao

Ercole Rao

Yadlapalli Venkateswara Rao

Bharathi Vasudeva Rao

 

Other publications of authors with the same name

Function inlining and loop unrolling for loop acceleration in reconfigurable processors., , , and . CASES, page 101-110. ACM, (2012)MatRIS: Multi-level Math Library Abstraction for Heterogeneity and Performance Portability using IRIS Runtime., , , , and . SC Workshops, page 1081-1092. ACM, (2023)Deffe: a data-efficient framework for performance characterization in domain-specific computing., , , and . CF, page 182-191. ACM, (2020)Ultra Low Latency Machine Learning for Scientific Edge Applications., , , , , and . FPL, page 1-7. IEEE, (2022)Retargetable automatic generation of compound instructions for CGRA based reconfigurable processor applications., , , and . CASES, page 4:1-4:9. ACM, (2014)Low Complex & High Accuracy Computation Approximations to Enable On-Device RNN Applications., , , , , , and . ISCAS, page 1-5. IEEE, (2019)Optimal SDRAM Buffer Allocator for Efficient Reuse of Layer IO in CNNs Inference Framework., , , , , and . ISCAS, page 1-5. IEEE, (2018)SAMOSA: Scratchpad aware mapping of streaming applications., , , , and . SoC, page 48-55. IEEE, (2011)Tiling Framework for Heterogeneous Computing of Matrix based Tiled Algorithms., , , , and . ExHET@PPoPP, page 1:1-1:6. ACM, (2023)Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials., , , , , , , , , and 7 other author(s). Int. J. High Perform. Comput. Appl., 37 (3-4): 351-379 (July 2023)