From post

Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance.

, , и . VDAT, том 7373 из Lecture Notes in Computer Science, стр. 357-359. Springer, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies., , , и . ISQED, стр. 665-669. IEEE, (2013)Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance., , и . VDAT, том 7373 из Lecture Notes in Computer Science, стр. 357-359. Springer, (2012)Phase Noise Analysis of Separately Driven Ring Oscillators., , , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (11): 4415-4428 (2022)A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime., , и . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 1557-1561 (2022)Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI., , , , , , , , , и 1 other автор(ы). IRPS, стр. 23-1. IEEE, (2022)Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals., , , , , и . IEEE Trans. Circuits Syst., 67-II (11): 2352-2356 (2020)Investigation of Body Bias Impact in Si/SiGe Heterojunction Line TFETs: A Physical Insight., и . ISCAS, стр. 1-5. IEEE, (2023)Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges., и . VLSID, стр. 12-13. IEEE Computer Society, (2015)Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications., , , , , , и . VLSID, стр. 292-296. IEEE, (2022)A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation., , , , , и . VDAT, стр. 1-6. IEEE, (2016)