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Disambiguation of "Dasygenis, Minas"

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A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System.

, , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (2): 546-558 (2008)

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Minas Pappas

Mark Minas

Minas Logothetis

Sabine Minas

Mark Minas

 

Other publications of authors with the same name

A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (3): 279-291 (2006)A distributed VHDL compiler and simulator accessible from the web.. PATMOS, page 1-7. IEEE, (2014)HLS Accelerated Noise Reduction Approach Using Image Stacking on Xilinx PYNQ., , and . MOCAST, page 1-4. IEEE, (2019)High Throughput Pipelined Implementation of the SHA-3 Cryptoprocessor., , and . ICM, page 1-4. IEEE, (2020)Σχεδιασμός πολύπλοκων ενσωματωμένων συστημάτων με χαμηλή κατανάλωση ισχύος και υψηλές επιδόσεις. Democritus University of Thrace, Greece, (2005)National Archive of PhD Theses: oai:10442/21025.An Efficient Method for Addressing COVID-19 Proximity Related Issues in Autonomous Shuttles Public Transportation., , , , and . AIAI (1), volume 646 of IFIP Advances in Information and Communication Technology, page 170-179. Springer, (2022)Accelerate Processing of Image with the Keccak-512 Algorithm on Cryptoprocessor., , , , and . SEEDA-CECNSM, page 1-4. IEEE, (2023)Acceleration of GANs for Potato Crop Disease Identification via FPGA., , , , and . SEEDA-CECNSM, page 1-4. IEEE, (2023)Autonomous Unmanned Ground Vehicle in Precision Agriculture - The VELOS project., , and . SEEDA-CECNSM, page 1-4. IEEE, (2022)Hardware Acceleration of SHA-256 Algorithm Using NIOS-II Processor., , and . MOCAST, page 1-4. IEEE, (2019)