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Disambiguation of "Kim, Byungsub"

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A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS.

, , , , and . IEEE J. Solid State Circuits, 44 (12): 3526-3538 (2009)

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Ky ng Kim

Die Artikelstruktur in passiven zweisprachigen Wörterbüchern Deutsch-Koreanisch: Konzeption zur Erstellung eines zweisprachigen Lernerwörterbuchs Deutsch-Koreanisch. Uni Heidelberg, (2008)

Kim Kressel

Sangho Kim

Youngmin Kim

Kim Redecker

 

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An Approximate Closed-Form Channel Model for Diverse Interconnect Applications., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (10): 3034-3043 (2014)An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (5): 1335-1344 (2015)A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (3): 142-146 (2013)A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (2): 91-95 (2013)A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation., , , and . IEEE J. Solid State Circuits, 48 (9): 2118-2127 (2013)A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement., , , , , and . IEEE J. Solid State Circuits, 51 (8): 1902-1914 (2016)Equalized on-chip interconnect: modeling, analysis, and design.. Massachusetts Institute of Technology, Cambridge, MA, USA, (2010)ndltd.org (oai:dspace.mit.edu:1721.1/58076).5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop., , , , and . ISSCC, page 94-95. IEEE, (2017)A 12-Gb/s AC-Coupled FFE TX With Adaptive Relaxed Impedance Matching Achieving Adaptation Range of 35-75Ω Z0 and 30-550Ω RRX., , and . A-SSCC, page 209-212. IEEE, (2018)A 20-Gb/s/pin 0.0024-mm2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces., , , , and . ISSCC, page 1-3. IEEE, (2022)