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Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias.

, , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 373-384 (2016)

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A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 406-407. IEEE, (2008)Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM., , , , , and . VLSIC, page 146-147. IEEE, (2012)Self-aligned Fiber Attach on Monolithic Silicon Photonic Chips: Moisture Effect and Hermetic Seal., , , , , , , , , and 6 other author(s). OFC, page 1-3. IEEE, (2023)Latest Progress and Challenges in 300 mm Monolithic Silicon Photonics Manufacturing., , , , , , , , , and 16 other author(s). OFC, page 1-3. IEEE, (2024)Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips., , , , , , , , , and . CICC, page 799-804. IEEE, (2007)3D-Split SRAM: Enabling Generational Gains in Advanced CMOS., , , , , , , , , and 6 other author(s). CICC, page 1-2. IEEE, (2021)Towards polarization insensitive photonic integrated circuits: polarization dependent loss reduction of CMOSintegrated monolithic SiPh components., , , , , , , , , and 26 other author(s). OFC, page 1-3. IEEE, (2024)Hybrid III-V laser integration on a monolithic silicon photonic platform., , , , , , , , , and 39 other author(s). OFC, page 1-3. IEEE, (2021)Monolithic Silicon Photonics., , , , , , , , , and 24 other author(s). BCICTS, page 263-269. IEEE, (2023)Polarization mode dispersion in CMOS-integrated monolithic SiPh components: simulations and experiments., , , , , , , , , and 42 other author(s). OFC, page 1-3. IEEE, (2023)