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A 1.2 V 300 μW second-order switched-capacitor Δ∑ modulator using ultra incomplete settling with 73 dB SNDR and 300 kHz BW in 130 nm CMOS., , and . ESSCIRC, page 271-274. IEEE, (2011)A Third-Order MASH $\Sigma \Delta $ Modulator Using Passive Integrators., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (11): 2871-2883 (2017)A Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators., , , and . PRIME, page 257-260. IEEE, (2023)A Fully Integrated and Reconfigurable Architecture for Coherent Self-Testing of High Speed Analog-to-Digital Converters., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (7): 1531-1541 (2011)A low power 4th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling., , and . ISCAS, page 1344-1347. IEEE, (2014)A simple 1 GHz non-overlapping two-phase clock generators for SC circuits., , and . MIXDES, page 174-178. IEEE, (2013)A second-order switched-capacitor ΔΣ modulator using very incomplete settling., , and . ISCAS, page 1367-1370. IEEE, (2011)Design methodology for Sigma-Delta modulators based on a genetic algorithm using hybrid cost functions., , , and . ISCAS, page 301-304. IEEE, (2012)Fully integrated and reconfigurable architecture for coherent self-testing of IQ ADCs., , , and . ISCAS, page 1927-1930. IEEE, (2010)15.3 A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣM., , and . ISSCC, page 274-275. IEEE, (2016)