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Disambiguation of "Liou, Jing-Jia"

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Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model.

, , , , , and . VLSI-DAT, page 1-4. IEEE, (2017)

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Jia-Jing Lee

Jia Jia

Konstantinos Lioupis

Aglaia Liourdi

Hwa-Meei Liou

 

Other publications of authors with the same name

Fast Statistical Timing Analysis By Probabilistic Event Propagation., , , and . DAC, page 661-666. ACM, (2001)Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models., , , , and . DAC, page 668-673. ACM, (2003)Pseudo-Multiple-Exposure-Based Tone Fusion With Local Region Adjustment., , , , , , and . IEEE Trans. Multim., 17 (4): 470-484 (2015)Diagnosis Framework for Locating Failed Segments of Path Delay Faults., and . IEEE Trans. Very Large Scale Integr. Syst., 16 (6): 755-765 (2008)AC-Plus Scan Methodology for Small Delay Testing and Characterization., , , , , , , , , and 2 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 21 (2): 329-341 (2013)Diagnosis framework for locating failed segments of path delay faults., , and . ITC, page 8. IEEE Computer Society, (2005)Delay testing considering crosstalk-induced effects., , , and . ITC, page 558-567. IEEE Computer Society, (2001)An efficient SAT-based path delay fault ATPG with an unified sensitization model., , and . ITC, page 1-7. IEEE Computer Society, (2007)A prototype of a wireless-based test system., , , , , , , , , and 2 other author(s). SoCC, page 225-228. IEEE, (2007)Design space exploration with a cycle-accurate systemC/TLM DRAM controller model., , , , , , and . VLSI-DAT, page 1-4. IEEE, (2017)