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Disambiguation of "Shanbhag, Naresh R."

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Low-power distributed arithmetic architectures using nonuniform memory partitioning.

, , and . ISCAS (3), page 470-473. IEEE, (1999)

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Naresh Yallapragada

Uma-Naresh Niranjan

Naresh Bikash Dasgupta

Naresh Reddy Thumati

Naresh Chandra Varshneya

 

Other publications of authors with the same name

A low-power bus design using joint repeater insertion and coding., and . ISLPED, page 99-102. ACM, (2005)Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers., and . ISLPED, page 334-339. ACM, (2001)A pipelined adaptive NEXT canceller., and . IEEE Trans. Signal Process., 46 (8): 2252-2258 (1998)A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training., , and . IEEE J. Solid State Circuits, 53 (11): 3163-3173 (2018)Analytical estimation of signal transition activity from word-level statistics., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (7): 718-733 (1997)Area-efficient high-throughput MAP decoder architectures., , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 921-933 (2005)Deep In-Memory Architectures in SRAM: An Analog Approach to Approximate Computing., , and . Proc. IEEE, 108 (12): 2251-2275 (2020)A sphere decoding approach for the vector Viterbi algorithm., , , and . ACSCC, page 114-118. IEEE, (2012)A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array., , and . ESSCIRC, page 263-266. IEEE, (2017)Low-power reconfigurable signal processing via dynamic algorithm transformations (DAT)., and . ICASSP, page 3081-3084. IEEE, (1998)