( en | de | ru )

 

Disambiguation of "Pezzarossa, Luca"

Author of the publication

copydeleteadd this publication to your clipboard
Using dynamic partial reconfiguration of FPGAs in real-Time systems.

, , , and . Microprocess. Microsystems, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Luca Tranchini

Luca Rizzini

Luca Tuninetti

Alfonz Luca

Marcello Lucà

 

Other publications of authors with the same name

An area-efficient TDM NoC supporting reconfiguration for mode changes., , and . NOCS, page 1-4. IEEE, (2016)Transitioning to Chisel in University Education: Experiences and Lessons Learned., and . NorCAS, page 1-7. IEEE, (2023)Dynamic nsNET2: Efficient Deep Noise Suppression with Early Exiting., , , , , , , , and . MLSP, page 1-6. IEEE, (2023)A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip., , , and . J. Syst. Archit., (2017)Interfacing hardware accelerators to a time-division multiplexing network-on-chip., , , and . NORCAS, page 1-4. IEEE, (2015)Reconfiguration in FPGA-based multi-core platforms for hard real-time applications., , and . ReCoSoC, page 1-8. IEEE, (2016)A Time-predictable TTEthenet Node., , , and . ISORC, page 229-233. IEEE, (2019)S4NOC: a minimalistic network-on-chip for real-time multicores., , and . NoCArc@MICRO, page 8:1-8:6. ACM, (2019)Towards a tailored mixed-precision sub-8-bit quantization scheme for Gated Recurrent Units using Genetic Algorithms., , , , , and . CoRR, (2024)A Multicore Processor for Time-Critical Applications., , and . IEEE Des. Test, 35 (2): 38-47 (2018)