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A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel., , , , , , , , , and . ISSCC, page 346-348. IEEE, (2011)A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers., , , , and . CICC, page 413-416. IEEE, (2006)An efficient transistor optimizer for custom circuits., , and . ISCAS (5), page 197-200. IEEE, (2003)A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS., , , , , and . IEEE J. Solid State Circuits, 40 (4): 986-993 (2005)A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File., and . ICCD, page 107-. IEEE Computer Society, (2003)A Case Study: Energy Efficient High Throughput Chip Multi-Processor Using Reduced-complexity Cores for Transaction Processing Workload., , , , and . Inf. Media Technol., 1 (1): 80-91 (2006)A leakage current replica keeper for dynamic circuits., , and . ISSCC, page 1755-1764. IEEE, (2006)A Reversible Poly-Phase Distributed VCO., and . ISSCC, page 2452-2461. IEEE, (2006)An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis., , and . VLSI Design, page 271-277. IEEE Computer Society, (2007)A sliding window scheme for accurate clock mesh analysis., , , , , , and . ICCAD, page 939-946. IEEE Computer Society, (2005)