Author of the publication

Runtime Power Management of 3-D Multi-Core Architectures Under Peak Power and Temperature Constraints.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (6): 905-918 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Temperature-aware energy minimization of 3D-stacked L2 DRAM cache through DVFS., , , and . ISOCC, page 475-478. IEEE, (2012)Exploiting maximum throughput in 3D multicore architectures with stacked NUCA cache., , and . VLSI-SoC, page 130-135. IEEE, (2011)Hybrid L2 NUCA Design and Management Considering Data Access Latency, Energy Efficiency, and Storage Lifetime., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (10): 3118-3131 (2016)Temperature-Aware Integrated DVFS and Power Gating for Executing Tasks With Runtime Distribution., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (9): 1381-1394 (2010)Cost-effective TSV redundancy configuration., , , , and . VLSI-SoC, page 263-266. IEEE, (2012)REDELF: An Energy-Efficient Deadlock-Free Routing for 3D NoCs with Partial Vertical Connections., , and . JETC, 12 (3): 26:1-26:22 (2015)Design and management of 3D-stacked NUCA cache for chip multiprocessors., , and . ACM Great Lakes Symposium on VLSI, page 91-96. ACM, (2011)THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures., , , and . ASP-DAC, page 773-778. IEEE, (2015)Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache., , , and . ISQED, page 163-170. IEEE, (2014)Fast estimation of software energy consumption using IPI(Inter-Prefetch Interval) energy model., , , , and . VLSI-SoC, page 224-229. IEEE, (2007)