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Disambiguation of "Lee, Se-Joong"

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A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip.

, , , , and . IEEE J. Solid State Circuits, 37 (10): 1352-1355 (2002)

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Yong-Joong Lee

Se-Joo Lee

Jung-Joong Lee

Yong-Se Lee

Joong Fang

 

Other publications of authors with the same name

81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (3): 370-383 (2009)Low energy transmission coding for on-chip serial communications., , and . SoCC, page 177-178. IEEE, (2004)A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes., , , , and . DATE, page 79-80. European Design and Automation Association, Leuven, Belgium, (2006)A 670 ps, 64 bit dynamic low-power adder design., , and . ISCAS, page 28-31. IEEE, (2000)A distributed crossbar switch scheduler for on-chip networks., , and . CICC, page 671-674. IEEE, (2003)A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip., , , , and . IEEE J. Solid State Circuits, 37 (10): 1352-1355 (2002)A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth., , , , , , , and . IEEE J. Solid State Circuits, 37 (5): 612-623 (2002)Packet-switched on-chip interconnection network for system-on-chip applications., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 52-II (6): 308-312 (2005)An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip., , , and . ISCAS (3), page 2357-2360. IEEE, (2005)On-chip network based embedded core testing., , , , , , and . SoCC, page 223-226. IEEE, (2004)