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Systematic Register Bypass Customization for Application-Specific Processors.

, , , , , , and . ASAP, page 64-74. IEEE Computer Society, (2003)

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Sentinel Scheduling for VLIW and Superscalar Processors., , , , and . ASPLOS, page 238-247. ACM Press, (1992)long version: TOCS 11(4): 376-408.In-Memory Data Parallel Processor., , and . ASPLOS, page 1-14. ACM, (2018)Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache., , , , , , and . CGO, page 179-190. IEEE Computer Society, (2005)Fine Grain Cache Partitioning Using Per-Instruction Working Blocks., , and . PACT, page 305-316. IEEE Computer Society, (2015)PEPSC: A Power-Efficient Processor for Scientific Computing., , , and . PACT, page 101-110. IEEE Computer Society, (2011)Uncovering hidden loop level parallelism in sequential applications., , , and . HPCA, page 290-301. IEEE Computer Society, (2008)WarpPool: sharing requests with inter-warp coalescing for throughput processors., , , , , , and . MICRO, page 433-444. ACM, (2015)Processor Acceleration Through Automated Instruction Set Customization., , and . MICRO, page 129-140. IEEE Computer Society, (2003)Code and data partitioning for fine-grain parallelism., and . LCTES, page 161-164. ACM, (2007)The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs., , , , and . ICPP (2), page 142-145. CRC Press, (1991)