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A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS., , , , , , , and . IEEE J. Solid State Circuits, 53 (4): 1038-1048 (2018)An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS., , , , , , , , , and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors., , , , , , , and . DAC, page 486-491. ACM, (2002)A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 42 (1): 233-242 (2007)A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 38 (11): 1866-1875 (2003)Dynamic sleep transistor and body bias for active leakage power control of microprocessors., , , , , and . IEEE J. Solid State Circuits, 38 (11): 1838-1845 (2003)Formal derivation of optimal active shielding for low-power on-chip buses., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (5): 821-836 (2006)Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (9): 1928-1933 (2006)SUB 45nm Low Power Design Challenges.. ISQED, page 4. IEEE Computer Society, (2007)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)