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Digital hilbert transformers for FPGA-based phase-locked loops., and . FPL, page 251-256. IEEE, (2008)Design of Optimal Multiplierless FIR Filters With Minimal Number of Adders., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (2): 658-671 (February 2023)Optimal Single Constant Multiplication Using Ternary Adders., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (7): 928-932 (2018)Resource Optimal Truncated Multipliers for FPGAs., , and . ARITH, page 102-109. IEEE, (2021)More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers., , , , , and . ISCAS, page 1-5. IEEE, (2023)Hardware-Aware Quantization for Multiplierless Neural Network Controllers., , , and . APCCAS, page 541-545. IEEE, (2022)Karatsuba with Rectangular Multipliers for FPGAs., , , , and . ARITH, page 13-20. IEEE, (2018)AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers., , , , , , and . CoRR, (2019)Table-Based versus Shift-And-Add Constant Multipliers for FPGAs., , , and . ARITH, page 151-158. IEEE, (2019)Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs., , , and . FCCM, page 75-83. IEEE, (2020)