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Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.

, , , , , and . MEMOCODE, page 181-187. IEEE Computer Society, (2007)

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Cell-aware analysis for small-delay effects and production test results from different fault models., , , , , , , and . ITC, page 1-8. IEEE Computer Society, (2011)Deterministic logic BIST for transition fault testing., , , and . IET Comput. Digit. Tech., 1 (3): 180-186 (2007)Computation and Application of Absolute Dominators in Industrial Designs., , and . ETS, page 137-144. IEEE Computer Society, (2007)PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits., , , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 306-315. Springer, (2000)Deterministic Logic BIST for Transition Fault Testing., , , and . ETS, page 123-130. IEEE Computer Society, (2006)Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates., and . European Test Symposium, page 1-6. IEEE Computer Society, (2012)Defect-oriented cell-internal testing., , , , , , , and . ITC, page 285-294. IEEE Computer Society, (2010)Implementing a Scheme for External Deterministic Self-Test., , , , and . VTS, page 101-106. IEEE Computer Society, (2005)Fault detection and diagnosis with parity trees for space compaction of test responses., , , , and . DAC, page 1095-1098. ACM, (2006)Synthesis of irregular combinational functions with large don't care sets., , , , and . ACM Great Lakes Symposium on VLSI, page 287-292. ACM, (2007)