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Understanding the Performance Benefit of Asynchronous Data Transfers in OpenCL Programs Executing on Media Processors., and . HiPC, page 135-144. IEEE Computer Society, (2015)ATTC (@C): Addressable-TLB based Translation Coherence., , , and . PACT, page 481-492. ACM, (2020)MicroRefresh: Minimizing Refresh Overhead in DRAM Caches., , and . MEMSYS, page 350-361. ACM, (2016)CHASM: Security Evaluation of Cache Mapping Schemes., , , , and . SAMOS, volume 12471 of Lecture Notes in Computer Science, page 245-261. Springer, (2020)HETEROGENEOUS ARCHITECTURE FOR SPARSE DATA PROCESSING., , , , , and . IPDPS Workshops, page 6-15. IEEE, (2022)Method to Determine Contrariety between Architectures Containing Stratified Memory Mapped Register Sets., , , , , , and . ISED, page 210-214. IEEE Computer Society, (2014)CSALT: context switch aware large TLB., , , , and . MICRO, page 449-462. ACM, (2017)Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB., , , and . ISCA, page 469-480. ACM, (2017)ANATOMY: an analytical model of memory system performance., , , and . SIGMETRICS, page 505-517. ACM, (2014)ExPress: Simultaneously Achieving Storage, Execution and Energy Efficiencies in Moderately Sparse Matrix Computations., , , , , and . MEMSYS, page 46-60. ACM, (2020)